#  WOSET 2019

For inquiries, please contact Sherief Reda
(sherief_reda@brown.edu)

[Agenda for the day](PDFs/2019/agenda.pdf)

To cite an article, please use this format:   
(author names here), "(article title here)", Article No. (article number here), Workshop on Open-Source EDA Technology (WOSET), 2019.


[Key Note Presentation: The New Golden Age of Open Silicon](PDFs/2019/keynote.pdf). 
Tim Edwards

[Article 1: Generic Logic Synthesis meets RTL Synthesis](PDFs/2019/a1.pdf).  
Tool: https://github.com/lsils/lstools-showcase <br /> 
Heinz Riener, Mathias Soeken, Eleonora Testa and Giovanni De Micheli

[Article 2: Skeletor Connector Language: Hierarchy Specification to HDL development made easy](PDFs/2019/a2.pdf). 
Tool: https://github.com/jaquerinte/Skeletor <br /> 
Ivan Rodriguez-Ferrandez, Guillem Cabo, Javier Barrera, Jeremy Giesen, Alvaro Jover-Alvarez and Leonidas Kosmidis

[Article 3: LNAST: A Language Neutral Intermediate Representation for Hardware Description Languages](PDFs/2019/a3.pdf).  
Sheng-Hong Wang, Akash Sridhar and Jose Renau

[Article 4: RTLog Framework: Yet another open HDL and compiler, this time for Relative-Timing design](PDFs/2019/a4.pdf).
Tool: https://github.com/VLSI-UTN-FRBA/RTLog <br />
Roberto Simone, Pablo D'Angelo, Ian Sztenberg, Francisco Javier Badenas, Francisco Dominguez, Agustin Ortiz, Guillermo Makar and Roberto Suaya

[Article 5: Approximate Logic Synthesis Using BLASYS](PDFs/2019/a5.pdf).  
Tool: https://github.com/scale-lab/BLASYS <br />
Jingxiao Ma, Soheil Hashemi and Sherief Reda

[Article 6: OpenROAD OpenDB Database Abstract](PDFs/2019/a6.pdf).  
Tool: https://github.com/The-OpenROAD-Project/OpenDB <br />
Tom Spyrou

[Article 7: LGraph: A Unified Data Model and API for Productive Open-Source Hardware Design](PDFs/2019/a7.pdf).  
Tool: https://github.com/masc-ucsc/livehd <br />
Sheng-Hong Wang, Rafael Trapani Possignolo, Qian Chen, Rohan Ganpati and Jose Renau

[Article 8: A unified memory compiler for synchronous and asynchronous circuits](PDFs/2019/a8.pdf).  
Tool: https://github.com/asyncvlsi/AMC <br />
Samira Ataei and Rajit Manohar

[Article 9: A Grid-based Technology-Independent Analog Cell Generator](PDFs/2019/a9.pdf).  
Arvind K. Sharma, Meghna Madhusudan, Kishor Kunal, Wenbin Xu, Yaguang Li, Tonmoy Dhar, Jitesh Poojary, Vidya A. Chhabria, Steven M. Burns, Parijat Mukherjee, Desmond A. Kirkpatrick, Jiang Hu, Ramesh Harjani and Sachin S. Sapatnekar

[Article 10: EvoApproxLib: Extended Library of Approximate Arithmetic Circuits](PDFs/2019/a10.pdf).  
Tool: https://ehw.fit.vutbr.cz/evoapproxlib/<br />
Vojtech Mrazek, Zdenek Vasicek and Lukas Sekanina

[Article 11: Latest Developments in the Xyce Large-Scale Analog Circuit Simulator](PDFs/2019/a11.pdf).  
Tool: https://xyce.sandia.gov <br />
Jason Verley, Eric R. Keiter and Heidi Thornquist

[Article 12: A Machine Learning Based Parasitic Extraction Tool](PDFs/2019/a12.pdf).  
Geraldo Pradipta, Vidya A. Chhabria and Sachin S. Sapatnekar

[Article 13: Fault, an Open Source DFT Toolchain](PDFs/2019/a13.pdf).  
Tool: https://github.com/Cloud-V/Fault <br />
Mohamed Gaber, Manar Abdelatty and Mohamed Shalan

[Article 14: Puffery: An Open-Source Benchmark Tool for PUFs](PDFs/2019/a14.pdf).  
Hunter Nichols and Matthew Guthaus

[Article 15: TherMOS: A Thermal model for analyzing self-heating in advanced MOSFETs](PDFs/2019/a15.pdf). 
Tool: https://github.com/VidyaChhabria/TherMOS <br />
Vidya A. Chhabria, Arvind K. Sharma, Meghna G. Mankalale, and Sachin S. Sapatnekar

[Article 16: An open road knows no borders: The contributions of UFRGS-UCSD partnership to the OpenROAD project](PDFs/2019/a16.pdf).  
Vitor Bandeira, Mateus Fogaça, Jiajia Li, Eder Matheus Monteiro, Isadora Oliveira, Ricardo Reis and Mingyu Woo

[Article 17: OpeNPDN: Neural Networks for Automated Power Delivery Network Synthesis](PDFs/2019/a17.pdf).  
Tool: https://github.com/The-OpenROAD-Project/OpeNPDN <br />
Vidya Chhabria, Andrew Kahng, Minsoo Kim, Uday Mallappa, Sachin Sapatnekar and Bangqi Xu

[Article 18: OGRE: Open-Source Global Router](PDFs/2019/a18.pdf).  
Tool: https://github.com/Cloud-V/OGRE <br />
Habiba Gamal, Ali El-Said, Fady Mohamed and Mohamed Shalan

[Article 19: Toward a digital flow for asynchronous VLSI systems](PDFs/2019/a19.pdf).  
Tool: http://github.com/asyncvlsi/act <br />
Samira Ataei, Yi-Shan Lu, Jiayuan He, Wenmian Hua, Sepideh Maleki, Yihang Yang, Rajit Manohar and Keshav Pingali