# WOSET 2021 Schedule
## November 4, 2021
All short paper videos in a given time slot will be shown sequentially followed by a 5 or 6 minute Q&A with the authors. Long paper videos in a given time slot will also be shown sequentially followed by a 6 minute Q&A with the authors. Poster presentations will last 5 minutes each.


# Short Papers

<table border="1">
<thead>
<tr>
<th>Time (GMT)</th>
<th>Time (PDT)</th>
<th>Article #</th>
<th>Author(s)</th>
<th>Title</th>
</tr>
</thead>
<tbody>
<tr>
<td rowspan=2>4:00 PM</td>
<td rowspan=2>9:00 AM</td>
<td>15</td>
<td>Healy, Yu, Dao, Chung, Koch</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-15">FABulous: an Open-Everything Framework for Embedded FPGAs</a></td>
</tr>
<tr>
<td>21</td>
<td>Dogan, Ugurdag, Guthaus</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-21">OpenCache: An Open-Source OpenRAM Based Cache Generator</a></td>
</tr>
<tr>
<td rowspan=2>4:15 PM</td>
<td rowspan=2>9:15 AM</td>
<td>14</td>
<td>Yuan, Shukla, Chetoui, Knox, Nemtzow, Reda,  Coskun</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-14">Towards Fast and Accurate Parallel Chip Thermal Simulations with PACT</a></td>
</tr>
<tr>
<td>22</td>
<td>Garg, Wang, Coffman, Renau</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-22">A Guide for Rapid Creation of New HDLs</a></td>
</tr>
<tr>
<td rowspan=3>4:30 PM</td>
<td rowspan=3>9:30 AM</td>
<td>9</td>
<td>Zeller</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-9">SystemVerilog IDE integration with Verible Language Server support</a></td>
</tr>
<tr>
<td>10</td>
<td>Fajardo, Laeufer, Bachrach, Sen</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-10">RTLFuzzLab</a></td>
</tr>
<tr>
<td>13</td>
<td>He, Hua, Lu, Maleki, Yang, Pingali, Manohar</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-13">interact: An Interactive Design Environment for Asynchronous Logic</a></td>
</tr>
</tbody>
</table>

# Long Papers 1

<table border="1">
<thead>
<tr>
<th>Time (GMT)</th>
<th>Time (PDT)</th>
<th>Article #</th>
<th>Author(s)</th>
<th>Title</th>
</tr>
</thead>
<tbody>
<tr>
<td rowspan=2>4:51 PM</td>
<td rowspan=2>9:51 AM</td>
<td>1</td>
<td>Callahan, Ansell, Bushagour, Green, Lattimore, Callaghan</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-1">CFU Playground: Build your own ML Processor using Open Source</a></td>
</tr>
<tr>
<td>2</td>
<td>Schwartz, Sharma, Rad, Takusagawa, Stoy, Nikhil</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-2">The Open-Source Bluespec bsc Compiler and Reusable Example Designs</a></td>
</tr>
<tr>
<td rowspan=2>5:21 PM</td>
<td rowspan=2>10:21 AM</td>
<td>11</td>
<td>Hasler, Muldrey, Hardy</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-11">A CMOS Programmable Analog Standard Cell Library in Skywater 130nm Open-Source Process</a></td>
</tr>
<tr>
<td>4</td>
<td>Edwards</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-4">Automating GDS Generation in Magic</a></td>
</tr>
<tr>
<td rowspan=2>5:51 PM</td>
<td rowspan=2>10:51 AM</td>
<td>5</td>
<td>Euphrosine, Springer</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-5">Porting software to hardware using XLS/DSLX</a></td>
</tr>
<tr>
<td>6</td>
<td>Eldridge, Barua, Chapyzhenka, Izraelevitz, Koenig, Lattner, Lenharth, Leontiev, Schuiki, Sunder, Young, Xia</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-6">MLIR as Hardware Compiler Infrastructure</a></td>
</tr>
<tr>
<td rowspan=2>6:21 PM</td>
<td rowspan=2>11:21 AM</td>
<td colspan=3>9 minute break</td>
</tr>
</tbody>
</table>

# Poster Presentations

<table border="1">
<thead>
<tr>
<th>Time (GMT)</th>
<th>Time (PDT)</th>
<th>Article #</th>
<th>Author(s)</th>
<th>Title</th>
</tr>
</thead>
<tbody>
<tr>
<td rowspan=4>6:30 PM</td>
<td rowspan=4>11:30 AM</td>
<td>17</td>
<td>Charan</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-17">Vezzal - a containerized tool to work with and test open source EDA tools</a></td>
</tr>
<tr>
<td>19</td>
<td>Chen, Edwards</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-19">Developing Open-Source Circuit Design and Flow Management Software</a></td>
</tr>
<tr>
<td>16</td>
<td>Mahintorabi</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-16">Software Inspired IC Hardware Workflows Using Bazel</a></td>
</tr>
</tbody>
</table>

# Long Papers 2

<table border="1">
<thead>
<tr>
<th>Time (GMT)</th>
<th>Time (PDT)</th>
<th>Article #</th>
<th>Author(s)</th>
<th>Title</th>
</tr>
</thead>
<tbody>
<tr>
<td rowspan=2>6:50 PM</td>
<td rowspan=2>11:50 AM</td>
<td>7</td>
<td>Berlstein, Nigam, Gyurgyik, Sampson</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-7">A Toolkit for Designing Hardware DSLs</a></td>
</tr>
<tr>
<td>12</td>
<td>Temple, Snelgrove, Neto, Gaillardon</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-12">LSOracle 2.0: Capabilities, Integration, and Performance</a></td>
</tr>
<tr>
<td rowspan=2>7:20 PM</td>
<td rowspan=2>12:20 PM</td>
<td>3</td>
<td>Laeufer, Bachrach, Sen</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-3">Open-Source Formal Verification for Chisel</a></td>
</tr>
<tr>
<td>8</td>
<td>Dobis, Petersen, Schoeberl</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-8">Towards Functional Coverage-Driven Fuzzing for Chisel Designs</a></td>
</tr>
<tr>
<td rowspan=2>7:50 PM</td>
<td rowspan=2>12:50 PM</td>
<td>20</td>
<td>Wang, Garg, Coffman, Mayer, Renau</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-20">A Parallel HDL Compilation Framework</a></td>
</tr>
<tr>
<td>23</td>
<td>Beamer, Nijssen, Pandian, Zhang</td>
<td><a href="https://woset-workshop.github.io/WOSET2021.html#article-23">ESSENT: A High-Performance RTL Simulator</a></td>
</tr>
</tbody>
</table>