# WOSET 2022 Schedule
## November 3, 2022

# Papers 1

<table border="1">
<thead>
<tr>
<th>Time (PST)</th>
<th>Duration (Minutes)</th>
<th>Article #</th>
<th>Author(s)</th>
<th>Title</th>
</tr>
</thead>
<tbody>
<tr>
<td>8:00 AM</td>
<td>20</td>
<td>12</td>
<td>Wijerathne, Li, Karunarathne, Mitra, Peh</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-12">Morpher: An Open-Source Integrated Compilation and Simulation Framework for CGRA</a></td>
</tr>
<tr>
<td>8:20 AM</td>
<td>20</td>
<td>20</td>
<td>Xu, Xiao, Luo, Liang</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-20">A MLIR-Based Hardware Synthesis Framework</a></td>
</tr>
<tr>
<td>8:40 AM</td>
<td>20</td>
<td>2</td>
<td>Euphrosine</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-2">Accelerate Silicon Design with Jupyter Notebooks</a></td>
</tr>
<tr>
<td>9:00 AM</td>
<td>20</td>
<td>10</td>
<td>Zhu, Yin, Wang, Tan</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-10">GreenRio: A Modern RISC-V Microprocessor Completely Designed with An Agile Open-source EDA Flow</a></td>
</tr>
<tr>
<td>9:20 AM</td>
<td>20</td>
<td>5</td>
<td>Goldstein, Edwards</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-5">Accessibility of Chip Design to the Non-Professional</a></td>
</tr>
<tr>
<td>9:40 AM</td>
<td>20</td>
<td>18</td>
<td>Liang, Edwards</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-18">IRSIM: A Switch-Level Simulator and Dynamic Power Analysis Tool</a></td>
</tr>
</tbody>
</table>

# Poster Presentations

<table border="1">
<thead>
<tr>
<th>Time (PST)</th>
<th>Duration (Minutes)</th>
<th>Article #</th>
<th>Author(s)</th>
<th>Title</th>
</tr>
</thead>
<tbody>
<tr>
<td rowspan=8>10:00 AM</td>
<td rowspan=8>60</td>

<td>4</td>
<td>Kashif, Ahmed, Karim</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-4">Bitstream Chef</a></td>
</tr>
<tr>
<td>6</td>
<td>Shahzaib, Kashif, Ahmed, Karim</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-6">SoC-Now: An Open-Source Web based RISC-V SoC Generator</a></td>
</tr>
<tr>
<td>7</td>
<td>Jia, Luo, Lu, Liang</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-7">TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra</a></td>
</tr>
<tr>
<td>8</td>
<td>Ahmed, Cirimelli-Low, Guthaus</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-8">OpenRegFile: Open-Source Register File Generation</a></td>
</tr>
<tr>
<td>13</td>
<td>Schoeberl, Pezzarossa</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-13">From Chisel to Chips with Open-Source Tools</a></td>
</tr>
<tr>
<td>16</td>
<td>Jayaraman, Huang, Renau</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-16">The Hardware Interchange Format
</a></td>
</tr>
<tr>
<td>17</td>
<td>Kemmerer</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-17">PipelineC: Easy open-source hardware description between RTL and HLS</a></td>
</tr>
</tbody>
</table>

# Papers 2

<table border="1">
<thead>
<tr>
<th>Time (PST)</th>
<th>Duration (Minutes)</th>
<th>Article #</th>
<th>Author(s)</th>
<th>Title</th>
</tr>
</thead>
<tbody>
<tr>
<td>11:00 AM</td>
<td>20</td>
<td>1</td>
<td>Birch</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-1">Open source FPGA-based emulation with Nexus</a></td>
</tr>
<tr>
<td>11:20 AM</td>
<td>20</td>
<td>11</td>
<td>Eriksson, Vora</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-11">A Java Backend for ESSENT</a></td>
</tr>
<tr>
<td>11:40 AM</td>
<td>20</td>
<td>19</td>
<td>Korbel</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-19">Rapid Open Hardware Development Framework</a></td>
</tr>
<tr>
<td>12:00 PM</td>
<td>20</td>
<td>3</td>
<td>Agostini, Curzel, Limaye, Amatya, Minutoli, Castellana, Manzano, Ferrandi, Tumeo</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-3">SODA Synthesizer: an Open-Source, End-to-End Hardware Compiler</a></td>
</tr>
<tr>
<td>12:20 PM</td>
<td>20</td>
<td>15</td>
<td>Hugg</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-15">8bitworkshop: An Interactive Verilog Learning Tool</a></td>
</tr>
<tr>
<td>12:40 PM</td>
<td>20</td>
<td>9</td>
<td>Manohar</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-9">xcell: a cell library characterizer for combinational and state-holding gates</a></td>
</tr>
<tr>
<td>1:00 PM</td>
<td>20</td>
<td>14</td>
<td>Nishizawa, Nakura</td>
<td><a href="https://woset-workshop.github.io/WOSET2022.html#article-14">Library characterizer for open-source VLSI design</a></td>
</tr>

</tbody>
</table>